The subject matter disclosed herein relates to digital radiographic (DR) detectors, in particular, to the use of amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistor (TFT) switching elements in the imaging pixels of a DR detector.
Mixed oxide semiconductor-based thin-film transistors (TFTs) for applications in active matrix displays (AMDS) has generated a body of experimental and theoretical studies, in particular to amorphous indium-gallium-zinc-oxide (a-IGZO). For applications in AMDS, reliability and stability of the TFTs used as pixel switching elements are of primary concern. Since the switching TFT of an AMD pixel is mostly biased negatively, while illuminated from the display backlight, stability against negative gate-bias stress and visible light illumination is of particular importance for commercialization. Although the effect of combined negative gate-bias and light illumination stress (NBIS) has been the focus of investigations and found to cause negative threshold-voltage (VTH) shift, ways of completely suppressing it have not yet been established. Since the TFT's VTH stability has a strong bearing on display uniformity, lifetime and pixel architecture, some researchers have proposed subjecting mixed oxide TFTs to post-deposition annealing at high temperatures under wet, oxygenated, ozonated, or nitrogenated environments as a way of minimizing the NBIS-induced instability. Others have proposed the use of light shields, nitrogen cap layers, high quality dielectrics (both as gate insulators and passivation layers), but such methods suppress the NBIS-induced instability to limited extents.
Recently, bulk-accumulation, which is achieved by the use of a dual-gate structure in which the top-gate and bottom-gate are electrically shorted together, has been shown to reduce the NBIS instability of mixed oxide TFTs with thin semiconductor layers (<25 nm). However, similar to other stability improvement methods, bulk accumulation also suppresses the NBIS instability to limited extents. There have been reports that have focused on the bias stability of mixed oxide TFTs and have indicated the importance of the semiconductor thickness in the stability of the TFTs. Some researchers have reported that the bias stability of the TFTs became better as semiconductor thickness increased, whereas others have reported that it worsened. Others showed opposite trends for wet annealed and un-annealed TFTs. For wet annealed TFTs, the VTH shift (ΔVTH) decreased with increasing semiconductor thickness and for un-annealed TFTs, ΔVTH increased with increasing semiconductor thickness. It was considered that the density of trap states increases with increasing semiconductor thickness in un-annealed TFTs, whereas in wet annealed TFTs, there is almost no bulk effect. Device structure and the type of dielectrics used may also be a source of the differences in the trends observed with varying semiconductor thickness. For instance, the stability of inverted staggered devices without a passivation layer is more likely to improve with increasing semiconductor thickness because the thicker the semiconductor, the further away is the front channel (bottom surface of the semiconductor layer) from the absorption/desorption processes occurring at the top surface. In addition to the possibility of varying the types and/or ratios of the component oxides, non-reproducibility and the abundance of conflicting mechanisms and theories published to explain the same phenomenon, make it even harder to understand these mixed oxide TFTs, let alone improve their stability.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.